The present invention relates to a programmable logic array for a semiconductor integrated circuit.
FIG. 1 is a block diagram for explaining the structure of a programmable logic array (to be referred to as a PLA hereinafter) used in a conventional semiconductor integrated circuit. Referring to FIG. 1, the PLA comprises, e.g., two logic matrices, i.e., an AND matrix 1 and an OR matrix 2. An input signal 3 consisting of c data signals is input to the rows of the AND matrix 1. The AND matrix 1 outputs d product term signals 4 from its columns, and inputs them to the columns of the OR matrix 2. An output signal 5 consisting of e data signals can be obtained from the rows of the OR matrix 2.
In the conventional PLA, if the size of the circuit changes depending on the input number (c), the product term number (d), and the output number (e), its shape changes two-dimensionally. When a plurality of PLAs are arranged on a chip, gaps are often formed therebetween, thus making high integration difficult and resulting in complex connections of input/output signal lines and a power source.